The present invention relates generally to integrated circuits and in particular to digital delay locked loops in semiconductor memory devices.
Semiconductor memory devices such as dynamic random access memory (DRAM) devices are widely used to store data in computers and electronic products. A DRAM device comprises a plurality of memory cells for storing data. A data is stored or written into a DRAM device by a write operation. The stored data is read from the DRAM device by a read operation.
During a read operation, a memory cell is accessed, the stored data is read from the memory cell and transmitted to an output pad. The data at the output pad is represented as an electrical signal or a data signal (DQ). In order to determine a time window in which a valid data is present at the output pad, a data strobe signal (DS) is designed to track or lock to the data signal. Locking, or synchronizing, the DS and DQ signals ensures the integrity of the data, which is especially essential in a high speed DRAM device.
When the DQ signal propagates from the memory cell to the output pad, a time delay occurs. It is difficult to predict the time delay of the DQ signal because of variations in temperature, supply voltage or other process variations within the DRAM device. Therefore locking the DS signal to the DQ signal requires careful timing calculation and reliable circuit design.
Different DRAM devices use different timing calculations and techniques for designing a circuit to lock the DS signal to the DQ signal. Some DRAM devices use analog circuits such as charge pump, loop filter and voltage-controlled delay line while other use a mix of analog and digital circuits for performing the necessary timing calculations. However, the inclusion of analog circuits often make it hard to scale for other process and applications and are unstable due to the variations in process, supply voltage and temperature. Furthermore, these analog implementations require complex tuning after the production in order to get a tight locking.
Thus, there is a need for a new technique which can more efficiently lock the strobe signal DS to the data signal DQ over wide range of frequency in integrated circuits. It is further desired that such circuits and method are portable and easy to scale for different process and applications without requiring post production tuning.
The problem associated with DLL and other problems are addressed by the present invention and will be understood by reading the following disclosure. A digital dual-loop delay locked loop (DLL) is provided which has a wide frequency lock range and tight locking without post production tunning. The digital dual-loop DLL is suitable for uses in a DRAM device to lock a strobe signal DS to a data signal.
In one embodiment, a dual-loop digital DLL is provided. The DLL includes a coarse loop to produce a first delayed signal which is coarsely locked to the input signal. The coarse loop has a delay range to provide a wide frequency lock range. The DLL further includes a fine loop connected to the coarse loop to produce a second delayed signal. The fine loop has a delay range which is substantially smaller than that of the coarse loop to provide a tight locking.
In yet another embodiment, a method for synchronizing two signals is described. The method includes applying an amount of delay to an input signal at a coarse loop to produce a first delayed signal. The method also includes applying an amount of small delay to the first delayed signal at a fine loop to produce an output signal. The method further includes comparing the output signal and the input signal and adjusting the delay of both loops until the output signal and the input signal are tightly synchronized.